Generally, in the manufacture of semiconductor devices, a transistor is fabricated according to following steps. First, a gate electrode is formed on a substrate and a source/drain region with shallow junction is formed through an ion implantation process using the gate electrode as a mask. Next, spacers are formed on sidewalls of the gate electrode and a source/drain region with deep junction is formed through an ion implantation using the spacers as a mask. As a result, a transistor comprising the gate electrode and an expanded source/drain region is formed in the substrate. The expanded source/drain region consists of the source/drain region with shallow junction as the lightly doped drain (LDD) region and the source/drain region with deep junction. Next, to reduce resistance during electrical operation of the transistor, a silicide layer is formed on the gate electrode and the surface of the substrate including the source/drain region. Here, the silicide layer is not formed on the spacers.
A prior approach is disclosed in U.S. Pat. No. 5,918,130 to Hause et al. that discloses a method for fabricating a transistor employing formation of silicide across a source/drain region prior to formation of the gate conductor. In particular, dopants are forwarded into a lateral region of a substrate to form an implant region. Then, a silicide layer and a sacrificial layer are formed respectively. A contiguous opening is formed through the sacrificial layer and the silicide layer, exposing a portion of the substrate. Dopants are then implanted into the exposed substrate region to form a channel. Spacers are formed on opposed sidewall surfaces of the sacrificial layer within the opening. A gate oxide is then formed across the exposed region, followed by the formation of a polysilicon gate conductor across the gate oxide. A polycide is formed across the gate conductor before the sacrificial layer is removed.
An alternate prior approach is disclosed in U.S. Pat. No. 6,087,235 to Yu, which discloses a method for fabricating a field effect transistor with elevated source/drain contact structures. A field effect transistor includes a drain extension implant, a source extension implant, a gate dielectric, a gate structure disposed over the gate dielectric, and a first spacer disposed on sidewalls of the gate dielectric and of the gate structure. An elevated drain contact structure is selectively grown on the drain extension implant and has a drain facetted surface facing toward the first spacer on the sidewall of the gate structure. Similarly, an elevated source contact structure is selectively grown on the source extension implant and has a source facetted surface facing toward the first spacer on the sidewall of the gate structure. A second spacer is formed to cover the drain facetted surface and the source facetted surface before dopant implantation into and silicide formation on the elevated drain and source contact structures.
FIGS. 1a through 1k illustrate, in cross-sectional views, the results of process steps for manufacturing a semiconductor device according to a known method.
Referring to FIG. 1a, a gate oxide layer 12 and a gate poly layer 14 are formed on a substrate 10 and a mask pattern 15 is formed over the gate poly layer 14.
Referring to FIG. 1b, the gate oxide layer 12 and the gate poly layer 14 are etched using the mask pattern 15 as an etching mask to form a gate electrode 16 comprising a gate poly pattern 14a and a gate oxide pattern 12a. 
As shown in FIG. 1c, an ion implantation is performed using the gate electrode 16 as a mask to form a source/drain region 18 with shallow junction adjacent to the gate electrode 16 in the substrate 10.
Referring to FIG. 1d, an insulating layer is deposited over the substrate 10 including the gate electrode 16. Then, an etch back process is performed for the insulating layer to form spacers 20 on sidewalls of the gate electrode 16.
Referring to FIG. 1e, an ion implantation is performed using the spacers 20 as a mask to form a source/drain region 22 with deep junction adjacent to the spacers 20 in the substrate 10. As a result, an expanded source/drain region 24 with an LDD region is formed in the substrate 10.
With reference to FIG. 1f, a metal layer 26 is formed over the substrate 10 including the gate electrode 16 and the spacers 20. The metal layer 26 is a multi-layer consisting of a titanium layer and a titanium nitride layer.
Referring to FIG. 1g, a first thermal treatment process is performed for the substrate 10 including the metal layer 26. By the thermal treatment, salicidation reaction occurs. As a result, a preliminary silicide layer 28a is formed on top of the gate electrode 16 and the surface of the substrate 10 including the source/drain region 24. However, the salicidation reaction does not occur in the metal layer 26 on the spacers 20 and, therefore, the preliminary silicide layer 28a is not formed on the spacers 20. The metal layer 26 unchanged on the spacers 20 is removed.
Referring to FIG. 1h, a second thermal treatment process is performed for the substrate 10 including the preliminary silicide layer 28a. As a result, the preliminary silicide layer 28a is changed into a silicide layer 28.
Referring to FIG. 1i, an insulating layer pattern 30 with contact holes 30a is formed over the substrate 10 including the silicide layer 28. Through the contact holes 30a, the silicide layer 28 on the gate electrode and some part of the silicide layer 28 on the substrate 10 including the source/drain region 24 are exposed.
Referring to FIGS. 1j and 1k, a barrier metal layer 32 is formed on bottom and sidewalls of the contact holes 30a. Then, the contact holes 30a are filled with conductive material and an etch back process is performed to form contact plugs.
Here, the spacers function as a mask for ion implantation. In addition, the silicide layer is not formed on the spacers. Such spacers are a necessary structure in manufacturing a semiconductor device but are unnecessary in respect of device operation. Particularly, the spacers may cause leakage during device operation. To obviate these shortcomings, a process omitting formation of the spacers has been developed. However, such a conventional method may increase electrical resistance in a device.